Dr. Michael Hußmann

Anschrift:

Michael Hußmann
Universität Paderborn
Institut für Informatik
Fakultät für Elektrotechnik,
Informatik und Mathematik
Fürstenallee 11
33102 Paderborn
Deutschland

Raum: F2.305
Tel.: +49 5251 60-
Fax: +49 5251 60-
e-mail: michaelh@upb.de

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Forschung

Lehre

• Projektgruppe "Automatische Nutzung von Multimedia-Befehlen auf rekonfigurierbaren Prozessor-Clustern"

Veröffentlichungen

TRETS09 Madhura Purnaprajna and Mario Porrmann and Ulrich Rückert and Michael Hußmann and Michael Thies and Uwe Kastens Run-Time Reconfiguration of Multiprocessors Based on Compile-Time Analysis In ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2009, accepted for publication.

Huß08 Michael Hußmann Compiler-Driven Dynamic Reconfiguration of Architectural Variants PhD thesis, University of Paderborn, April 2008

WASP07 Michael Hußmann and Michael Thies and Uwe Kastens and Madhura Purnaprajna and Mario Porrmann and Ulrich Rückert Compiler-Driven Reconfiguration of Multiprocessors In Proceedings of the Workshop on Application Specific Processors (WASP) 2007 held in conjunction with the Embedded Systems Week, 2007 (CODES+ISSS, EMSOFT, and CASES), October 2007

DHTK07 Ralf Dreesen and Michael Hußmann and Michael Thies and Uwe Kastens Register Allocation for Processors with Dynamically Reconfigurable Register Banks In Proceedings of the 5rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 5rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2007), March 2007

HTK05d Michael Hußmann, Michael Thies, and Uwe Kastens SALT: Efficient Load-Time Scheduling for Superscalar Processor Families Using Compiler Annotations Technical Report tr-ri-05-263, University of Paderborn, October 2005

HTK05c Michael Hußmann, Michael Thies, and Uwe Kastens Compact Annotations for Efficient Load-Time Scheduling Technical Report tr-ri-05-262, University of Paderborn, October 2005

HTK05b Michael Hußmann, Michael Thies, and Uwe Kastens Parallelizing Compilation through Load-Time Scheduling for a Superscalar Processor Family In Proceedings of the 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 3rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2005), March 2005

HTK05a Michael Hußmann, Michael Thies, and Uwe Kastens Parallelizing Compilation through Load-Time Scheduling for a Superscalar Processor Family Technical Report tr-ri-05-255, University of Paderborn, February 2005

Huß04 Michael Hußmann Parallelisierende Übersetzung durch load-time scheduling für eine superskalare Prozessorfamilie Master's thesis, University of Paderborn, June 2004

Huß02 Michael Hußmann Transformation von Java-Bytecode für die Verifikation auf Chip-Karten Bachelor's thesis, University of Paderborn, July 2002

Preise

• 15.02.2003: Preis der Fakultät für Elektrotechnik, Informatik und Mathematik 2003
• 29.01.2005: Preis der Fakultät für Elektrotechnik, Informatik und Mathematik 2005